1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a sense amplifier control circuit for a semiconductor memory device.
2. Description of Conventional Art
FIG. 1 illustrates the construction of a conventional semiconductor memory. As shown therein, the semiconductor memory includes a plurality of cell arrays, i, j, k, l, m, . . . in which data are recorded; a plurality of word line drivers (only one of which has been illustrated for the sake of clarity) which receive an input row address and drive a corresponding word line; a plurality of sense amplifier (amp) arrays . . . , S/Ai, S/Aj, S/Ak, S/Al, S/Am, . . . , each of which is formed of a plurality of sense amps amplifying the data loaded in the word line which has been driven; a column decoder which decodes an input column address identifying the column of a selected memory cell and outputs a column address selecting signal YSEL; a column block decoder which generates a column block selecting signal . . . . , CBSELi, . . . ,CBSELm, . . . to select a specific block or memory cell array based on a bank address in the memory address; S/A local input/output lines . . . . , SAIOi, . . . ,SAIOm, . . . and inverse S/A local input/output lines . . . , SAIOBi, . . . ,SAIOBm, . . . ; data bus input/output lines DBIO1, DBIO0B, DBIO1, DBI01B which transmit the data loaded in the selected word line and bit line; and a plurality of switches . . . , SWi, SWBi, . . . , SWm, SWBm, . . . for selectively connecting corresponding S/A and inverse S/A local input/output lines SAIO and SAIOB with data bus lines DBIO and DBIOB in accordance with the column block selecting signals CBSELs.
FIG. 2 illustrates a circuit diagram of a sense amplifier SA in a sense amplifier array S/A in FIG. 1. As shown, the sense amp SA includes a bit line connecting circuit 10 for connecting the bit line BL0 and the bit bar line BL0B (also known as a complementary bit line) to the S/A and inverse S/A local input/output lines SAIO and SAIOB, respectively, in response to the column address selecting signal YSEL for a column corresponding to the sense amp SA. The bit line connecting circuit 10 includes a first NMOS transistor MN1 having its drain connected to the bit line BL0, its source connected to the S/A local input/output line SAIO and its gate receiving the column address selecting signal YSEL. A second NMOS transistor MN2 has its drain connected to the bit bar line BLOB, its source connected to the inverse S/A local input/output line SAIOB and its gate receiving the column address selecting signal YSEL. Together, the first and second NMOS transistors MN1 and MN2 are commonly referred to as a Y-gate.
With reference to the accompanying drawings, the operation of the thus constructed conventional semiconductor memory will be described. Operation will be described for the case of writing or reading data in a memory cell having a memory address P. When a word line driver for a row in the kth memory cell array, which contains the memory cell with address P, is driven based on a row address signal (/RAS signal), a couple of sense amps SAk,m and SAI,m, adjacent to the kth cell array, operate and load data in corresponding bit and bit bar lines (SAk,m represents the sense amp in the kth sense amp array and in the mth column position).
Next, when the column operation is initiated, the mth column address selecting signal mYSEL is driven by the column decoder, and accordingly first and second transistors MN1, MN2 (FIG. 2) in each of the sense amps SAs in the mth column are turned on and connect a corresponding bit and bit bar line with the S/A and inverse S/A local input/output lines SAIO and SAIOB.
Also, the kth column block selecting signal CBSELk is driven by the column block decoder, and accordingly the kth and Ith S/A and inverse S/A local input/output lines SAIOk, SAIOBk, SAIOI and SAIOBI are connected with the data bus lines DBIO1, DBIO1B, DB100 and DB100B via the selected switches SWk, SWBk, SWI, SWBI. As shown in FIG. 1, even though only the kth column block selecting signal CBSELk goes high, an OR-gate network distributes the kth column block selecting signal CBSELk to both the corresponding kth memory cell array and the subsequent Ith memory cell array. Consequently, the kth switches SWk and SWBk corresponding to both the kth memory cell array and the kth sense amp array S/Ak and the Ith switches SWI and SWBI corresponding to both the Ith memory cell array and the Ith sense amp array S/Al connect the S/A and inverse S/A local input/output lines SAIO and SAIOB with the data bus lines DBIO and DBIOB.
Since the mth column address selecting signal mYSEL is directly connected with the first and second transistors MN1 and MN2 of the sense amps SA in the mth column as shown in FIG. 2, all of these sense amps operate. However, only the kth and Ith switches SWk, SWBk, SWI, and SWBI are selected by the kth column block selecting signal CBSELk; and therefore, each of the S/A and inverse S/A local input/output lines SAIO and SAIOB for the sense amps other than sense amps SAk,m and SAI,m are not connected with the data bus input/output lines DBIO and DBIOB.
In the above-described conventional system, since the column address selecting signal mYSEL is commonly connected with the first and second NMOS transistors MN1 and MN2 of the sense amps SAs in that column, even in the event of reading or writing the data in the cell array k, all the sense amps SA in the mth column turn on.
Thus, for example, the sense amps SAi,m, SAj,m, SAk,m, SAI,m and SAm,m transmit data to the corresponding S/A and inverse S/A local input/output lines SAIO and SAISOB; thereby consuming an unnecessary amount of current. Furthermore, if for some reason the sense amps SAs do not operate, precharge voltages of the bit line and data line collide with each other and current consumption occurs. Particularly, as the capacity of a memory becomes larger, current consumption becomes greater. In addition, as loading of the column address selecting signal becomes greater in accordance with the increase in memory capacity, a rise and fall time of the column address selecting signal decreases and the speed of the memory is reduced. Therefore, considerable amounts of current are consumed.